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v silicon proven PLL IP hard core
  Ø High speed low jitter PLL IP with medium input frequency base on CHRT 0.13um
     generic CMOS process
    Haokai_PLL_130CHRT_01                            
      l FEATURES:
              > PFD input frequency range: 10 MHz to 400 MHz   
              > Output frequency range: 25 MHz to 1.0 GHz
              > Operating voltage range: 1.08 V to 1.32 V
              > Operating junction temperature: -40ºC to125ºC
              > Area: 309 µm ×332 µm
              > Pre-divider ratios: 1, 2, 4, 8
              > Loop-divider Dy range: 2 to 32
              > Built-in loop filter
              > Power-down mode
              > Built-in lock detection
              > Built-in ring oscillator
              > By-pass mode
              > Power range: 2 mA to 9 mA
     l APPLICATIONS: 
              > Clock multiplication, clock generation
     l TECHNOLOGY: 
              > CHRT 0.13 µm generic CMOS
              > 1 Poly; 6 or upper Metals layers
     l STATUS:
              > Silicon proven
     l JITTERS:
              > Peak-to-peak period jitter:25 ps 
              > RMS period jitter:3 ps
                                                            ......>>>more 

   Ø High speed low jitter PLL IP with medium high input frequency base on CHRT
     0.13um generic CMOS process
    Haokai_PLL_130CHRT_02                         
      l FEATURES:
              > PFD input frequency range: 0.5 MHz to 250 MHz  
              > Output frequency range: 20 MHz to 1.0 GHz
              > Operating voltage range: 1.08 V to1.32 V
              > Operating junction temperature: -40 º C to125 º C
              > Area: 405 µm ×314 µm
              > Pre-divider ratios: 1, 2, 4, 8, 16, 32, 64, 128
              > Loop-divider Dy range: 1 to 511
              > Built-in loop filter
              > Power-down mode
              > Built-in lock detection
              > Built-in ring oscillator
              > By-pass mode
              > Power range: 2 to 10 mA
     l APPLICATIONS: 
              > Clock multiplication, clock generation
     l TECHNOLOGY: 
              > CHRT 0.13 µm generic CMOS
              > 1 Poly; 6 or upper Metals layers
     l STATUS:
              > Silicon proven
     l JITTERS:
              > Peak-to-peak period jitter:25 ps 
              > RMS period jitter:3.5 ps
                                                            ......>>>more

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