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v silicon proven PLL IP hard core
Ø High speed low jitter PLL IP with high input frequency base on SMIC 0.13um
generic CMOS process
Haokai_PLL_130SMIC_05
l FEATURES:
> PFD input frequency range: 50 MHz to 400 MHz
> Output frequency range: 80 MHz to 2 GHz
> Operating voltage range: 1.08 V to 1.32 V
> Operating junction temperature: -40ºC to125ºC
> Area: 260 µm Х 235 µm
> Pre-divider ratios: 1, 2, 4, 8, 16, 128
> Loop-divider Dy range: 2 to 32
> Built-in loop filter
> Power-down mode
> Built-in lock detection
> Built-in ring oscillator
> By-pass mode
> Power range: 4mW to 14mW
l APPLICATIONS:
> Clock multiplication, clock generation
l TECHNOLOGY:
> SMIC 0.13 μm generic CMOS
l STATUS:
> Silicon proven on MPW
l JITTERS:
> Peak-to-peak period jitter: 23 ps
> RMS period jitter:2.5 ps
......>>>more
Ø High speed low jitter PLL IP with high input frequency base on SMIC 0.13um
generic CMOS process
Haokai_PLL_130SMIC_06
l FEATURES:
> PFD input frequency range: 5 MHz to350 MHz
> Output frequency range: 50 MHz to 800 MHz
> Operating voltage range: 1.08 V to 1.32 V
> Operating junction temperature: -40 º C to125 º C
> Area: 260 μm Х 235 μm
> Pre-divider ratios: 1, 2, 4, 8, 16, 128
> Loop-divider Dy range: 2 to 32
> Built-in loop filter
> Power-down mode
> Built-in lock detection
> Built-in ring oscillator
> By-pass mode
> Power range: 3 mW to 9mW
l APPLICATIONS:
>Clock multiplication, clock generation
l TECHNOLOGY:
>SMIC 0.13 μm generic CMOS
l STATUS:
> Silicon proven on MPW
l JITTERS:
> Peak-to-peak period jitter: 22 PS
> RMS period jitter:3.5 PS
......>>>more page 1 2 3 4 5 6 7 8 9 10 next page
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