About  Haokai
 
Company Introduction
  Management Team
  Successful Cases

 


   Dr. Cangsang Zhao, CEO, founder: 

Cangsang Zhao obtained his B.S. and M.S. degrees in Physics from Peking University in 1998 and 1991, respectively. He later obtained his Ph.D. degree in Electrical Engineering from Oregon Graduate Institute of Science & Technology in 1996. Between 1996 and 2005, he has been worked in Intel holding senior design engineer, design manager, and senior design manager etc. positions. In that period, He was involved in the design of Intel’s advanced microprocessors including Pentium III, Pentium 4, and Pentium 4 dual core. In early 2005, he founded Haokai Microelectronics (Shanghai) Corporation in Shanghai, China.

Cangsang holds 4 U.S. patents with 4 other patents pending in IC design area. He authored 10 technical papers and co-authored 4 other technical papers. He accumulated Extensive design experience in the area of analog circuits (PLLs, DLLs, VRMs), digital circuits (SRAM, high-speed I/O buffers, ESD, power delivery, and clock distribution etc.), and process technologies (0.18-um, 0.13-um, 0.09-um, and 0.065-um CMOS).

   Dr. Feng Wang, CTO, co-founder: 

Feng Wang obtained his B.S. degree in Physics from Peking University in 1998. In 1996, He obtained his M.S. degree in Electrical Engineering and Ph.D. degree in Physics from Purdue University. Between 1996 and 2005, he worked as a senior design engineer in Intel’s microprocessor design center, accumulated 9 years of design experience on analog and mixed-signal circuits. In that period, He was involved in the design of Intel’s advanced microprocessors including Pentium II, Pentium III, Pentium 4, Pentium 4 dual core, and Centurio n processor. In early 2005, he co-founded Haokai Microelectronics (Shanghai) Corporation in Shanghai, China.

Feng holds 3 U.S. patents with 6 other patents pending in IC design area. He accumulated Extensive design experience in the area of analog circuits (PLLs, DLLs), high-speed digital circuits (high-speed I/O buffers, clock distribution, and mixed-signal circuit testability circuits etc.).