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   Core Business: Phase-locked loop (PLL) SIP

v  High-speed phase-locked loop(PLL) SIP

        

 l  PFD input frequency range: 0.5 MHz to 400 MHz

 l  Output frequency range:20 MHz to 3000 MHz

 l  Typical RMS/peak-to-peak jitter at high frequency: 3 ps/20ps

 l  Built-in loop filter, built-in lock detection, built-in ring oscillator

 l  Phase adjustable clock outputs (phase step is as fine as 1/320 cycle)

 l  Process, voltage, and temperature independency

 l  Large divider range: 1-4096

 

 

v  silicon proven PLL IP hard core

 

series of smic 0.13um

 

Ø  High speed low jitter PLL IP with low input frequency base on SMIC 0.13um mixed signal     CMOS process

Ø  High speed low jitter PLL IP with medium high input freqwuency base on SMIC 0.13um     mixed signal CMOS process

Ø  High speed low jitter PLL IP with high input frequence base on SMIC 0.13um mixed signal     CMOS process

Ø  High speed low jitter PLL IP with low input frequency base on SMIC 0.13um generic CMOS     process

Ø  High speed low jitter PLL IP with medium high input frequence base on SMIC 0.13um           generic CMOS process

Ø  High speed low jitter PLL IP with high input frequence base on SMIC 0.13um generic CMOS     process

 

series of CHRT

 

Ø  High speed low jitter PLL IP with medium high input frequence base on CHRT 0.13um     generic CMOS process

Ø  High speed low jitter PLL IP with medium input frequence base on CHRT 0.13um generic     CMOS process

    

series of smic 90nm

 

Ø  High speed low jitter PLL IP with low input frequency base on SMIC 90nm generic CMOS     process

Ø  High speed low jitter PLL IP with medium high input frequence base on SMIC 90nm generic     CMOS process

Ø  High speed low jitter PLL IP with high input frequence base on SMIC 90nm generic CMOS     process

v  PLL IP in progress

 

series of CHRT

 

Ø  High speed low jitter PLL IP with medium high input frequence base on CHRT 0.18um      generic CMOS process

 

v  PLL IP in testing

 

series   of   FPGA /SMIC

 

Ø  low jitter FPGA PLL with phase tuning adjustment

 

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